The present invention relates to a packet transfer method and a packet transfer control circuit. More particularly, the present invention pertains to an optimal packet transfer method for a packet transfer control circuit having a serial interface that complies with the IEEE 1394 standard.
Serial interfaces complying with the IEEE 1394 standard are used to connect digital video cameras, which store a large amount of audio and visual data, and peripheral equipment, such as color page printers, to personal computers. FIG. 1 shows a first prior art example of a network system connecting a plurality of apparatuses. A plurality of IEEE 1394 bus cables 1 connect nodes A1–G1 to one another. The nodes A1–G1 each represent, for example, a computer-related apparatus such as a personal computer, a monitor, a digital video camera, or a printer.
Referring to FIG. 1, the nodes B1, A1, C1, E1, G1, F1 are connected in series and the node D1 is connected to the node C1. The nodes A1–G1 each have a packet transfer control circuit (not shown) for performing packet transfer.
The transfer of data in a network having the topology or layout of FIG. 1 will now be described using an example of when the node A1 transfers data to the node B1 while the node E1 transfers data to the node F1.
The node A1 transfers packet “ab”, which is addressed to the node B1, to the nodes B1, C1. The node B1 determines that the packet ab is addressed to it upon reading the information of a header included in the packet ab. The node B1 acquires the data stored in the packet ab. Although the node C1 also receives the packet ab, the node C1 determines that the packet ab is addressed to another node upon reading the header information and transfers the packet ab downstream to the nodes D1, E1. In the same manner, the node E1 transfers the packet ab to the further downstream node G1, which in turn, transfers the packet ab to the node F1. In this manner, the packet ab is transferred to all of the nodes including the non-addressee nodes C1, D1, E1, G1, F1 in addition to the addressee node B1.
The node E1 transfers a packet “ef”, which is addressed to the node F1, to the nodes C1, G1. The node G1 determines that the packet ef is addressed to another node upon reading the information of a header included in the packet ef and transfers the packet ef to the downstream node F1. The node F1 determines that the packet ef is addressed to it upon reading the header information and acquires the data stored in the packet ef. The node C1 determines that the packet ef has been addressed to another node upon reading the header information of the packet ef and transfers the packet ef to the downstream nodes A1 and D1. In the same manner, the node A1 transfers the packet ef to the further downstream node B1. Thus, the packet ef is transferred to the non-addressee nodes A1, B1, C1, D1, G1 in addition to the addressee node F1. The bus cables 1 are entirely occupied by the two packets ab, ef which are transferred alternately as shown in FIG. 2.
As a second prior art example, a network having the topology shown in FIG. 3 will be described. The network of FIG. 3 is, for example, used in a television conference system. Nodes A2–G2 and nodes PCa–PCg are connected to one another by bus cables 1. Each of the nodes PCa–PCg is a terminal device, such as a personal computer. Each of the nodes A2–G2 is a conference-related device, such as an input device or a display device.
The nodes A2–G2 are connected to the devices PCa–PCg, respectively. The nodes PCa–PCg are each connected to a server 2. The nodes A2–G2 and PCa–PCg are laid out about the server 2. The nodes A2–G2, PCa–PCg each have a packet transfer control circuit (not shown) for performing packet transfer.
The topology of FIG. 3 will now be described using an example of when the data input to the node A2 is displayed at the nodes B2–G2. The node A2 transfers a packet A·PCa, which includes the input data, to the node PCa. The node PCa processes the data of the packet A·PCa and generates a packet PCa·PC(b–g), which includes the processed data. The node PCa transfers the packet PCa·PC(b–g) to the nodes PCb–PCg by way of the server 2. The nodes PCb–PCg each process the data of the packet PCa·PC(b–g) to respectively generate packets PCb·B, PCc·C, PCd·D, PCe·E, PCf·F, PCg·G, which include the newly processed data and are transferred to the associated nodes B2–G2.
In this case, the packet A·PCa is transferred to the nodes B2–G2 via the node PCa, the server 2, and the nodes PCb–PCg. The node PCa determines that the packet A·PCa has been addressed to it upon reading the information of a header included in the packet A·PCa and acquires the data stored in the packet A·PCa to generate the processed data. The node PCa then transfers the packet PCa·PC(b–g), which includes the data addressed to the nodes PCb–PCg, to the nodes B2–G2 via the corresponding nodes PCb–PCg and to the node A2. The nodes PCb–PCg each recognize that the packet PCa·PC(b–g) is addressed to them by reading the information of a header included in the packet PCa·PC(b–g) and acquire the data to generate the newly processed data. The node PCb transfers the packet PCb·B, which includes the data addressed to the node B2, to the nodes A2, C2–G2 via the corresponding nodes PCa, PCc–PCg in addition to the node B2. The node B2 determines that the packet PCb·B has been addressed to it upon reading the header information in the packet PCb·B and acquires the data stored in the packet PCb·B.
Subsequently, in the same manner, the nodes PCc–PCg transfer packets PCc·C, PCd·D, PCe·E, PCf·F, PCg·G addressed to the nodes C2–G2. Accordingly, eight packets are required for a single transfer cycle as shown in FIG. 4.
As described above, in the first and second prior art examples, packets that need only be transferred between certain nodes are transferred to all of the nodes. This substantially decreases data transfer speed when a large amount of data is transferred simultaneously.